In general, in semiconductor integrated circuit devices, signals inside and outside a semiconductor chip should be synchronized in time in order to accurately transmit/receive the signals inside and outside the semiconductor chip. In such synchronization, usually, an internal clock (or internal strobe) signal whose transition timing is accurately controlled is generated in order to maintain a constant timing relationship with transition timing of a clock (or strobe) signal inputted from the outside of the semiconductor chip, and the internal clock signal is utilized for acquiring a data signal.
An object, of the phase synchronization circuit mentioned above is to adjust the timing at the transmission/reception of the signals inside and outside the chip to minimize an undesired influence such as miss-acquisition of data value. In general, as to the time until phases are synchronized, it is desired that the phase synchronization is completed in a shorter time.
Meanwhile, for the purpose of reducing the semiconductor chip cost, it is preferable that the circuit is realized with the smallest possible occupying area on the chip or with the smallest possible number of elements and gates.
When applications to mobile devices or utilization of low-cost package are considered, it is desirable that the circuit is operated by lower electric power (electric power at the time of operation and standby).
As a technology relating to such a phase synchronization circuit, for example, the following technologies are disclosed.
In “IEEE Journal of Solid-State Circuits” (U.S.), November 1996, vol. 31, No. 11, pp. 1656-1668 (Non-Patent Document 1), two delay lines FDA and BDA are arranged in parallel in opposite directions, a control circuit MCC is arranged therebetween in parallel with them, and a load circuit having the same delay time as that of a clock driver connected to an output of the delay line BDA is designed as a dummy in advance so as to connect with an input of the delay line FDA. This circuit detects a position where phases are synchronized in the delay line FDA based on the delay line FDA and the control circuit MCC, and inputs a clock from the same position in the delay line BDA to transmit the clock in a direction opposite to the delay line FDA. As a result, high-speed synchronization where phases are synchronized in the delay of two cycles is realized.
Japanese Patent Application Laid-Open Publication No. 2002-152018 (Patent Document 1) discloses an example where a variable delay element and a fixed delay element are combined to form a synchronization circuit with a small number of delay tiers. The variable delay element controls a power source voltage so as to change its delay time.
In both Non-Patent Document 1 and Patent Document 1, the delay time created in the synchronization circuit is controlled so that transition (rise or fall) timings of signals of inside and outside are aligned only at a timing equal to a clock cycle of a reference signal given as an input or a timing which is integral multiple of the clock cycle.